The present invention generally relates to semiconductor memory devices and more particularly to a random access memory providing a reliable contact for interconnections.
The technique of multilevel interconnection has been used commonly in the recent semiconductor integrated circuits having increased integration density. In using such a multilevel interconnection, there is a tendency that the steps or irregularities formed on the upper surface of the multilevel interconnection tend to have an increased step height because of the large number of layers and interconnection patterns embedded in the multi-level interconnection. Thereby, such an increased step height causes various reliability problem particularly for the interconnection patterns provided on the top surface of the multilevel interconnection structure.
In order to fill the depressions and to form a planarized upper surface, the use of so-called SOG (spin-on-glass) has been proposed and used widely. In this technique, an organic solution of silicon is applied on the surface of the insulation layer and cured by evaporating the solvents. This technique, although effective in planarizing the surface of an insulator layer, tends to cause a problem of defective interconnections when the interconnection pattern such as aluminum pattern is provided in contact directly with the SOG layer. It is believed that organic vapors as well as the water vapor that are released from the SOG causes such a degradation of the contact. It should be noted that SOG generally releases volatile components even after the curing. Because of this reason, an insulation layer such as silicon oxide or PSG is provided further on the SOG layer by the CVD process to support the interconnection pattern such that the interconnection pattern is separated from the SOG layer.
In relation to such a conventional multilevel interconnection wherein an SOG layer is covered by a silicon oxide or other insulating layer for supporting the interconnection patterns, a structure is proposed in the U.S. patent application Ser. No. 495,514, now U.S. Pat. No. 5,068,711 and in the U.S. patent application Ser. No. 712,378, now U.S. Pat. No. 5,155,064 that is a divisional application of Ser. No. 495,514, wherein the assignee is the same assignee of the present invention. In this proposal, an elevating structure is formed in correspondence to the region where the contact hole is to be formed such that the surface of the insulator layer underlying the SOG layer projects upward from the upper major surface of the SOG layer. Thereby, the insulator layer underlying the SOG layer contacts directly with the insulator layer provided on the SOG layer in correspondence to the region where the contact hole is to be formed, and the SOG layer is excluded from the contact hole. In other words, the SOG layer is not exposed at the side wall of the contact hole and a reliable electric contact is achieved.
When applying this previous proposal to the DRAMs (Dynamic Random Access Memories), one has to solve various problems.
FIG. 1 shows the overall construction of a conventional DRAM chip 10.
Referring to FIG. 1, the surface of the DRAM chip 10 is divided into a number of generally rectangular regions by the peripheral circuits 11 that are arranged along a zone extending laterally and vertically throughout the chip 10. In the illustrated example, the zones cross with each other generally at a central part of the chip 10. In each rectangular region thus divided, a number of columnar zones 12 are provided to extend vertically in the drawing with a regular interval for accommodating the sense amplifiers S/A. Adjacent to the zones 12, memory cells (not shown specifically in FIG. 1) are provided in the row and column formation to form a memory cell region.
In correspondence to each column of the memory cells, a word line WL is provided to extend vertically as shown in FIG. 1. Further, in correspondence to each row of the memory cells, complementary bit lines BL and BL are provided to extend laterally as shown in FIG. 1. Further, each sense amplifier in the zone 12 is connected to the sense amplifiers on the same row of other columns via a data bus line DB that extends laterally through the chip 10. The data bus line DB thereby extends in the row direction and connects the sense amplifiers S/A aligned on the same row to the peripheral circuit 11. It should be noted that there are a number of data bus lines DB extending laterally across the surface of the chip.
FIG. 2 shows a typical construction of a part of the memory cell, wherein the memory cell includes a plurality of transistor T11, T13, T22, . . . arranged in rows and columns. There, the transistors T11 and T13 are connected commonly to a bit line BL extending in the row direction, while the transistor T22 is connected to another, complementary bit line BL. Further, each transistor is connected to a corresponding word line WL1, WL2, WL3, . . . More specifically, the transistor T11 has a source connected to the bit line BL. Similarly the transistor T13 has a source connected to the same bit line BL. The transistor T22 on the other hand has a source connected to the complementary bit line BL. Further, the transistors T11, T22, T13 have respective drains connected to the memory cell capacitor. The word lines WL1-WL3 are connected to the respective gates of the transistors T11, T22, T13.
FIG. 3 shows the circuit diagram of the sense amplifier S/A.
Referring to FIG. 3, the sense amplifier includes P-channel MOS transistors Q1 and Q3 as well as N-channel MOS transistors Q2 and Q4, wherein the transistors Q1 and Q2 are connected in series to form a first path while the transistors Q3 and Q4 are connected in series to form a second path. The sense amplifier S/A is formed by connecting the first path and the second path in parallel between a supply voltage Vcc and another supply voltage Vss.
In the sense amplifier, it will be understood that the bit line BL is connected commonly to the respective drains of the transistors Q1 and Q2 and further to respective gates of the transistors Q3 and Q4. The bit line BL, on the other hand, is connected to the respective drains of the transistors Q3 and Q4, and further to the respective gates of the transistors Q1 and Q2. Thereby, the bit lines BL and BL has to cross with each other in the region of the sense amplifier S/A.
FIG. 4 shows such a crossing of the bit lines BL and BL in the sense amplifier S/A. Here, the bit line BL is connected once to a conductor strip located underneath the bit line by a contact hole. As will be described later, this conductor strip is formed at the time of formation of the word line WL as a part of the conductor layer forming the word line WL. On the other hand, the complementary bit line BL extends over the conductor pattern, separated of course by an insulation layer not illustrated, and the crossing of the bit line BL and BL is achieved as illustrated.
FIG. 5 shows a cross sectional view of the conventional DRAM including the memory cell region and the sense amplifier region, wherein the sense amplifier region shows the cross section taken along the line 5--5' of FIG. 4.
Referring to FIG. 5, the DRAM is constructed on a device region that is defined on the upper major surface of a silicon substrate 21 by a field oxide region 22.
As usual, a gate electrode 23 of polysilicon is provided on the device region with a gate oxide film 23a intervening between the gate electrode 23 and the upper major surface of the substrate 21, and a silicon oxide layer 24 is provided for example by the CVD process to bury the gate electrode 23 underneath. It should be noted that the gate electrode 23 is formed as a part of the word line WL that is extending through the DRAM chip 10. As shown in FIG. 1, there are a number of word lines WL extending parallel, and the cross section of FIG. 5 shows another word line WL that extends over the field oxide region 22.
On the silicon oxide layer 24, another silicon oxide layer 25 is provided. The silicon oxide layers 24 and 25 are formed with a contact hole that exposes the upper major surface of the substrate 21 in correspondence to a diffusion region 21a acting as a source of the memory cell transistor, and a polysilicon electrode 26 is provided to extend from the upper major surface of the diffusion region 21a along the upper major surface of the silicon oxide layer 25 to form the bit line BL. The electrode 26 extends obliquely to the plane of the drawing and shows an appearance in the illustration of FIG. 5 that the electrode 26 is interrupted at an intermediate position, covering the silicon oxide layer 25 only partially. Further, the polysilicon electrode 26 is covered by a silicon oxide film 27 that buries the electrode 26 as well as the silicon oxide layer 25 underneath. On the field oxide region 22, it will be seen thereby that a consecutive deposition of the silicon oxide layers 24, 25 and 27 is made such that these layers bury the polysilicon word line WL on the field oxide region 22.
In the layered structure of layers 24, 25 and 27, there is formed a through hole 24a that exposes the upper major surface of the diffusion region 21b acting as a drain of the memory cell transistor, and there is formed a polysilicon electrode 28 that extends upward along the side wall of the through hole 24a and spreads laterally at a level above the silicon oxide layer 27 to form a stacked capacitor C characterized by a large surface area. The electrode 28 is covered by a thin dielectric film 28a such as silicon oxide (not shown), and a ground electrode 29 of polysilicon covers the fin part of the electrode 28. Between the ground electrode 29 that covers the rear or lower surface of the fin part of the electrode 28 and the upper major surface of the silicon oxide layer 27, there may be provided a silicon nitride film 30 for protecting the silicon oxide layer 27 from etching at the time of forming the fin structure.
Further, in order to provide the multi-level interconnection, an insulation layer 31 of PSG (phosphosilicate glass) or BPSG (boro-phosphosilicate glass) is provided to extend throughout the chip 10. Thus, the insulation layer 31 extends also over the sense amplifier region 12. The structural feature and the problem of the sense amplifier region 12 will be examined later in detail.
Referring again to FIG. 5, particularly the memory cell region, there are provided aluminum interconnection patterns on the insulation layer 31 with a regular interval to form a word bus line WB. Here, the word bus line WB is used for distributing the word line voltage efficiently over the memory cells on the chip and establishes a contact with the polysilicon word line at a suitable contact hole.
The word bus line WB is buried under an insulation layer 34 such as PSG or BPSG that in turn is provided on an SOG layer 35 that fills the depressed regions formed between the word bus lines WB. Thereby, the SOG layer 35 improves the planarization of the insulation layer 34. On the insulation layer 34, the data bus line DB shown in FIG. 1 is provided for interconnection with the sense amplifiers.
Referring now to the sense amplifier region of FIG. 5, the insulation layer 31, the SOG layer 35 and the insulation layer 34 are provided in correspondence to the memory cell region. There, an aluminum pattern 33 is provided on the insulation layer 31 in correspondence to the word bus lines WB, and the data bus line DB establishes a contact with the aluminum pattern 33 via a contact hole 34a that penetrates through the layer 34 as well as the SOG layer 35. The aluminum pattern 33 in turn is connected to the sense amplifier at a site not shown in FIG. 5.
In such a conventional DRAM device, there has been a problem of unreliable contact of the data bus line DB and the aluminum pattern 33 because of the SOG layer 35 exposed at the side wall of the contact hole 34a. When the contact hole 34a is filled by aluminum, which may be conducted typically by the sputtering process, the SOG layer 35 may release the organic vapors and water due to the heating associated with the deposition, and the contact between the data bus line DB and the aluminum pattern 33 may be deteriorated.
In the plan view of FIG. 4, this contact hole 34a is generally formed between a pair of bit lines extending parallel with other. As shown in the cross sectional view of FIG. 5, each of the parallel bit lines includes a first conductor strip 23' that is formed simultaneously with the word line WL by patterning a common polysilicon layer, and a second conductor strip 26' that is formed simultaneously with the bit lines BL and BL by patterning a common polysilicon layer. As the aluminum pattern 33 is provided on the lowest part of the insulation layer 31 located between a pair of ridges corresponding to the polysilicon patterns 23' and 26', there occurs an accumulation of the SOG on the upper major surface of the pattern 33, and this accumulated SOG layer is exposed at the side wall of the contact hole 34a.
Now, the reason of accumulation of the SOG layer on the aluminum interconnection pattern 33 and the adverse effect of such an SOG layer are thus clarified, one may think that the problem would be eliminated by simply providing the interconnection pattern 33 not on the depressed part of the insulation layer 31 but on the projected part thereof, that is, on the part located immediately above the electrodes 23' and 26'. This solution, however, cannot be adopted, as the design rule for the polysilicon electrodes such as the electrodes 23, 23', 26, 26' is substantially more strict than the design rule of the aluminum pattern 33 as well as the word line buses WB. For example, the bit lines BL, BL and the word lines WL are patterned within the accuracy of .+-.0.5 .mu.m as for the positional deviation, while the word line bus WB or data bus DB is usually patterned with the accuracy of .+-.1 .mu.m. Thereby, there is no guarantee that the aluminum pattern 33 is formed exactly on the highest level part of the insulation layer 31. When failed, the accumulation of the SOG layer on the aluminum pattern 33 occurs more or less and the reliable contact cannot be achieved.